In recent years, the field of logical circuits and integrated semiconductor stores in bipolar technology has been marked by brisk progress which in technical literature has become known as MTL (Merged Transistor Logic) or I.sup.2 L (Integrated Injector Logic). Attention is drawn to the articles in the IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pp. 340 ff and 346 ff. In addition, such storage cells are known from U.S. Pat. Nos. 3,736,477 and 3,816,758. Further, this technology (MTL or I.sup.2 L) and its various applications has been described in a number of U.S. Patents and Publications, a number of which are identified below:
U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1974 to S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,886,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating A Semiconductor Memory System" granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith.
IBM Technical Disclosure Bulletin publication entitled "I.sup.2 L/MTL Storage Cell Layout:" by H. H. Berger et al., Vol. 22, No. 10, March 1980, pages 4604-5.
IBM Technical Disclosure Bulletin publication (GE 8-77-0015) entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1, June 1978, pages 231-2.
"Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 340-6.
"Integrated Injection Logic: A New Approach to LSI" by Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 346-51.
"I.sup.2 L Takes Bipolar Integration A Significant Step Forward" by R. L. Horton et al., Electronics Feb. 6, 1975, pages 83-90.
"I.sup.2 L Puts It All Together For 10-bit a-d converter Chip" by Paul Brokaw, Electronics/Apr. 13, 1978, pages 99-105.
"Integrated Injection Logic Shaping Up As Strong Bipolar Challenge to MOS", Electronic Design 6, Mar. 15, 1974, pages 28 and 30.
Storage concepts with bipolar transistors have short switching times and are particularly suitable for the design of extremely highly integrated stores and logic circuit arrays (PLA's).
Stores comprising MTL-structured bipolar transistors necessitate a recharging of bit data and/or control line capacitances for selecting a storage cell. During that process, the voltage swing of the bit lines approximately equals the voltage swing of the selected word lines. As previously described in German Patent No. 2 511 518 (U.S. Pat. No. 4,090,255), the capacitive discharge currents are discharged to ground via the storage cells of the selected word line and via word line drivers. In highly integrated store matrices with a greater number of storage cells this has the disadvantage that the area requirements of the driver circuits, the electric power dissipation for each driver and the delay time during word line selection become excessive. Thus the advantages inherent in the MTL structure are partly offset.
To eliminate this disadvantage, German Offenlegungsschrift No. 28 55 866 (U.S. Pat. No. 4,280,198), proposes a method of driving a semiconductor storage and a circuit arrangement which do not have these shortcomings. The method is characterized in that prior to selection and in response to a selection signal, control signals from a control circuit known per se are simultaneously applied to a discharge circuit, common to all storage cells, and to switching transistors which are thus switched on, and in that the discharge currents of the line capacitances on the bit data and control lines flow through the switching transistors, being jointly discharged via the discharge circuit.
Although it is possible with this discharge method to use the minimum swing on the word line to prevent capacitive peak currents on the voltage supply lines and to obtain a relatively high degree of integration, these solutions have the following disadvantages.
The selection operation and the discharge operation of the bit lines must be effected sequentially. The increase in the sense current from the sense circuit after bit line selection decisively determines the access time to the storage cell. The bit and word line potential transistors operating in parallel must be switched on at the end of the selection time, thus increasing the cycle time of the store chip.
In addition, the peripheral circuits of a store thus designed still require a great number of components. The read signal emitted depends upon the direct current supplied by the read/write amplifier. To obtain a higher and steeper read and write signal, to reduce the number of control lines as well as the number of components required for the read/write circuits. German Patent Application No. P 29 26 050.2 (U.S. Pat. No. 4,330,853) proposes a method for reading and writing which is characterized in that the current required for reading and/or writing the storage cells is generated by discharging the injector capacitances of the nonaddressed storage cells and is directly applied to the addressed storage cells for reading and/or writing. The bit line discharge currents occurring are used to read and/or write a selected storage cell of the respective bit line pair. The discharge currents of the bit line and injector junction capacitances of the non-selected storage cells charge the injector diffusion capacitances of the selected cell. During this process, these diffusion capacitances are discharged via internal cell currents, discharge on the OFF side of the storage cell being effected much more rapidly than on the ON side, so that the read signal is the difference signal derived from the charges on the OFF and the ON side being discharged at different speeds. A relatively high read signal is obtained by operating the MTL storage cells by means of very low injector currents during reading. In this current range the current gain of cell pnp transistors has not yet noticeably decreased, so that a considerable proportion of the current flowing into the ON side of the cell is reinjected, thus generating the read signal. Although the proportion of the reinjected current compared to the total current injected into the ON side is relatively high, the absolute reinjection current is low. This leads to a read signal with a rather shallow edge.
As a result, the access time for a store thus operated is relatively long and the operating reliability depends relatively strongly on the tolerances of the circuit components.
Therefore, it is the object of the invention to provide a circuit arrangement for capacitive read signal amplification of an integrated semiconductor store with storage cells consisting of flip-flops with bipolar transistors in MTL technology, which by influencing the two recharge currents acting on the selected bit lines, considerably improves the leading edge of the read signal, reduces the tolerance dependence of circuit components and improves the access time by about 20 percent.